Sub-micron sized transistors are very well known and are used extensively in all types of electrical devices. It is also well known that these transistors include a gate electrode that overlaps isolation regions on opposite ends of the gate width. As is well accepted by semiconductor manufacturers, electrical contact is made to these transistors by way of an electrical contact plug that extends through an overlying dielectric layer or pre-metal dielectric layer (PMD).
Due to concerns related to minimizing damage to the delicate gate oxide layer that isolates the gate electrodes from the underlying channel region, manufacturers have been careful to place the electrical contacts on that portion of the gate electrodes that overlap the substantially thicker isolation regions. This deliberate placement of the electrical contacts over the isolation regions assures manufacturers that any potential damage to the gate oxide that might occur during use of the dry (plasma) etches, which are often used to form the openings for the electrical contacts, is minimized. When exposed to such dry etch processes, a charge build-up can occur that can severely damage the gate oxide. This concern has remained very much intact, particularly given how device sizes, and correspondingly gate oxide thicknesses, have continued to shrink from one device generation to the next. As such, manufacturers have continued to contact the gates over the isolation regions.